Profile Control Of Gate Structures In Semiconductor Devices

ABSTRACT

An integrated circuit (IC) with active and dummy device cell arrays and a method of fabricating the same are discloses. The IC includes a substrate, an active device cell, and a dummy device cell. The active device cell includes an array of source/drain (S/D) regions of a first conductivity type disposed on or within the substrate and an array of gate structures with a first gate fill material disposed on the substrate. The dummy device cell includes a first array of S/D regions of the first conductivity type disposed on or within the substrate, a second array of S/D regions of a second conductivity type disposed on or within the substrate, and an array of dual gate structures disposed on the substrate. Each of the dual gate structures includes the first gate fill material and a second gate fill material that is different from the first gate fill material.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.17/320,171, titled “Profile Control of Gate Structures in SemiconductorDevices,” filed May 13, 2021, which claims the benefit of U.S.Provisional Patent Application No. 63/136,972, titled “Gate Layout forNMOS and PMOS and the Method for Forming the Same,” filed Jan. 13, 2021,each which is incorporated by reference herein in its entirety.

BACKGROUND

With advances in semiconductor technology, there has been increasingdemand for higher storage capacity, faster processing systems, higherperformance, and lower costs. To meet these demands, the semiconductorindustry continues to scale down the dimensions of semiconductordevices, such as metal oxide semiconductor field effect transistors(MOSFETs), including planar MOSFETs and fin field effect transistors(finFETs). Such scaling down has increased the complexity ofsemiconductor manufacturing processes.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of this disclosure are best understood from the followingdetailed description when read with the accompanying figures.

FIGS. 1A-1J illustrate top-down and cross-sectional views of active anddummy cells of an integrated circuit, in accordance with someembodiments.

FIGS. 1K-1O illustrate top-down and cross-sectional views of active anddummy cell arrays of an integrated circuit, in accordance with someembodiments.

FIGS. 2A-2J illustrate top-down and cross-sectional views of active anddummy cells of an integrated circuit, in accordance with someembodiments.

FIGS. 2K-2M illustrate isometric views of active and dummy cells of anintegrated circuit, in accordance with some embodiments.

FIG. 3 is a flow diagram of a method for fabricating active and dummycells of an integrated circuit, in accordance with some embodiments.

FIGS. 4A-13G illustrate cross-sectional views of active and dummy cellsof an integrated circuit at various stages of their fabrication process,in accordance with some embodiments.

FIG. 14 is a flow diagram of another method for fabricating active anddummy cells of an integrated circuit, in accordance with someembodiments.

FIGS. 15A-22C illustrate cross-sectional views of active and dummy cellsof another integrated circuit at various stages of their fabricationprocess, in accordance with some embodiments.

Illustrative embodiments will now be described with reference to theaccompanying drawings. In the drawings, like reference numeralsgenerally indicate identical, functionally similar, and/or structurallysimilar elements. The discussion of elements with the same annotationsapplies to each other, unless mentioned otherwise.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the processfor forming a first feature over a second feature in the descriptionthat follows may include embodiments in which the first and secondfeatures are formed in direct contact, and may also include embodimentsin which additional features may be formed between the first and secondfeatures, such that the first and second features may not be in directcontact. As used herein, the formation of a first feature on a secondfeature means the first feature is formed in direct contact with thesecond feature. In addition, the present disclosure may repeat referencenumerals and/or letters in the various examples. This repetition doesnot in itself dictate a relationship between the embodiments and/orconfigurations discussed herein.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper,” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. The spatially relative termsare intended to encompass different orientations of the device in use oroperation in addition to the orientation depicted in the figures. Theapparatus may be otherwise oriented (rotated 90 degrees or at otherorientations) and the spatially relative descriptors used herein maylikewise be interpreted accordingly.

It is noted that references in the specification to “one embodiment,”“an embodiment,” “an example embodiment,” “exemplary,” etc., indicatethat the embodiment described may include a particular feature,structure, or characteristic, but every embodiment may not necessarilyinclude the particular feature, structure, or characteristic. Moreover,such phrases do not necessarily refer to the same embodiment. Further,when a particular feature, structure or characteristic is described inconnection with an embodiment, it would be within the knowledge of oneskilled in the art to effect such feature, structure or characteristicin connection with other embodiments whether or not explicitlydescribed.

It is to be understood that the phraseology or terminology herein is forthe purpose of description and not of limitation, such that theterminology or phraseology of the present specification is to beinterpreted by those skilled in relevant art(s) in light of theteachings herein.

In some embodiments, the terms “about” and “substantially” can indicatea value of a given quantity that varies within 5% of the value (e.g.,±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examplesand are not intended to be limiting. The terms “about” and“substantially” can refer to a percentage of the values as interpretedby those skilled in relevant art(s) in light of the teachings herein.

The fin structures disclosed herein may be patterned by any suitablemethod. For example, the fin structures may be patterned using one ormore photolithography processes, including double-patterning ormulti-patterning processes. Double-patterning or multi-patterningprocesses can combine photolithography and self-aligned processes,allowing patterns to be created that have, for example, pitches smallerthan what is otherwise obtainable using a single, directphotolithography process. For example, a sacrificial layer is formedover a substrate and patterned using a photolithography process. Spacersare formed alongside the patterned sacrificial layer using aself-aligned process. The sacrificial layer is then removed, and theremaining spacers may then be used to pattern the fin structures.

The present disclosure provides example integrated circuits (ICs) withactive and dummy device cell arrays in respective active and dummydevice areas, and example methods of fabricating the same. The exampleIC can include n- and/or p-type active device cell arrays. The n-typeactive device cell arrays can include arrays of active n-type cells(N-cells). Each of the active N-cells can include one or moreelectrically active n-type FETs (NFETs; e.g., NMOSFETs, N-finFETs, orgate-all-around (GAA) NFETs) and/or n-type structures, such as n-typesource/drain (S/D) regions and n-type metal gate (NMG) structures withn-type gate metal fill (e.g., n-type work function metal (nWFM)).

The p-type active device cell arrays can include arrays of active p-typecells (P-cells). Each of the active P-cells can include one or moreelectrically active p-type FETs (PFETs; e.g., PMOSFETs, P-finFETs, orgate-all-around (GAA) PFETs) and/or p-type structures, such as p-typeS/D regions and p-type metal gate (PMG) structures with p-type gatemetal fill (e.g., p-type WFM (nWFM)). The active N-cells and P-cells canfurther include contact structures disposed on one or more S/D regionsand gate structures. The contact structures can electrically couple theone or more S/D regions and gate structures to power supplies.

The term “N-cell” (also referred to as “N-device cell”) is used hereinto refer to a cell that includes NFET(s) and/or NMG structure(s) anddoes not include PFET(s) and/or PMG structure(s). The term “P-cell”(also referred to as “P-device cell”) is used herein to refer to a cellthat includes PFET(s) and/or PMG structure(s) and does not includeNFET(s) and/or NMG structure(s). The term “NP-cell” (also referred to as“NP-device cell”) is used herein to refer to a cell that includes bothNFET and PFET and/or both NMG and PMG structures.

The dummy device cell arrays can be disposed adjacent to or surroundingthe active device cell arrays and can include electrically inactive(“dummy”) N-cells and P-cells, and/or NP-cells. Unlike the activeN-cells and P-cells, the dummy N-cells, P-cells, and NP-cells do notinclude contact structures and/or contact landing pads or regions on theS/D regions and/or gate structures. In some embodiments, the dummyN-cells and P-cells can have gate structures similar to that of therespective active N-cells and P-cells.

The dummy device cell arrays can be formed and arranged in a manner toachieve a substantially uniform surface profile across the gatestructures in both types of active device cell arrays. A non-uniformsurface profile across the gate structures can result in a gate heightmismatch between the gate structures in the active device cell arrays,and consequently degrade the IC performance. To achieve thesubstantially uniform surface profile in both types of active devicecell arrays, each dummy device cell array can be formed with a gatesurface area ratio of about 1:1 between the total top surface area ofthe dummy NMG structures and the total top surface area of the dummy PMGstructures in the dummy device cell array. Such balanced gate surfacearea ratio between the dummy NMG and PMG structures can prevent orminimize the “dishing” caused by the chemical mechanical polishing (CMP)processes during the formation of the active NMG and PMG structures inthe active device cell arrays. The dishing effect can be due to thedifferent polishing rates between the gate structures in the dummy andactive device cell arrays when the dummy device cell arrays have onetype of gate structures, such as polysilicon gate structures, NMGstructures, and PMG structures. The polishing rates can be different forthe different materials of polysilicon gate structures, NMG structures,and PMG structures. Thus, a balanced distribution of the two types ofgate structures in the dummy device cell arrays provide matchingpolishing rates for each type of gate structures in the active devicecell arrays, and consequently prevent or minimize the CMPprocess-related dishing effects.

In some embodiments, each of the dummy device cell arrays can be formedwith an equal number of dummy N-cells and P-cells to achieve thebalanced gate surface area ratio. In some embodiments, the dummy N-cellsand P-cells can be arranged in an array configuration or in analternating configuration with respect to each other. The dummy N-cellscan have dummy NMG structures that are equal in number to the dummy PMGstructures of the dummy P-cells. In some embodiments, the dummy NMG andPMG structures can have gate dimensions (e.g., gate length, gate width,and gate height) that are substantially equal to each other. In someembodiments, the dummy NMG structures can have a total top surface areathat is substantially equal to the total top surface area of the dummyPMG structures. In some embodiments, each of the dummy device cellarrays can be formed with arrays of NP-cells having an equal number ofdummy NFETs and PFETs and/or an equal number of dummy NMG and PMGstructures to achieve the balanced gate surface area ratio. In someembodiments, adjacent dummy NMG structures can be separated by an n-typeS/D region and adjacent dummy PMG structures can be separated by ap-type S/D region. In some embodiments, adjacent dummy NMG structuresand adjacent dummy PMG structures can be separated by the sameconductivity type (e.g., n- or p-type) S/D region.

FIGS. 1A-1C illustrate top-down views of an active P-cell 102P, anactive N-cell 102N, and a dummy NP-cell 102NP, respectively, of an IC(not shown), according to some embodiments. FIGS. 1D-1F illustratecross-sectional views of active P-cell 102P, active N-cell 102N, anddummy NP-cell 102NP along lines A-A, B-B, and C-C of FIGS. 1A-1C,according to some embodiments. FIGS. 1G-1J illustrate cross-sectionalviews of active P-cell 102P, active N-cell 102N, and dummy NP-cell 102NPalong lines D-D, E-E, F-F, and G-G of FIGS. 1A-1C, according to someembodiments. FIGS. 1D-1J illustrate cross-sectional views withadditional structures that are not shown in FIGS. 1A-1C for simplicity.The discussion of elements in FIGS. 1A-1J with the same annotationsapplies to each other, unless mentioned otherwise.

Referring to FIGS. 1A-1J, active P-cell 102P, active N-cell 102N, anddummy NP-cell 102NP can be disposed on different regions of a substrate104 of the IC. Active P-cell 102P and active N-cell 102N can be disposedin active device areas of the IC and dummy NP-cell 102NP can be disposedin a dummy device area of the IC. In some embodiments, active P-cell102P, active N-cell 102N, and dummy NP-cell 102NP can be arranged in arow or column on substrate 104, and dummy NP-cell 102NP can be disposedbetween active P-cell 102P and active N-cell 102N. Unlike active P-cell102P and active N-cell 102N, dummy NP-cell 102NP is not electricallycoupled to any power supply and is electrically isolated from otherstructures of the IC. In some embodiments, the IC can include any numberof active P-cell 102P, active N-cell 102N, and dummy NP-cell 102NP. Insome embodiments, dummy NP-cells, such as dummy NP-cell 102NP, can bedisposed surrounding one or more of active P-cell 102P and/or activeN-cell 102N.

Substrate 104 can be a semiconductor material, such as silicon,germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI)structure, other suitable semiconductor materials, and a combinationthereof. Further, substrate 104 can be doped with p-type dopants (e.g.,boron, indium, aluminum, gallium, or other suitable p-type dopants) orn-type dopants (e.g., phosphorus, arsenic, or other suitable n-typedopants).

Referring to FIGS. 1A, 1D, and 1G, in some embodiments, active P-cell102P can include (i) a well region 106P disposed within substrate 104,(ii) an array of S/D regions 110P disposed within well region 106P,(iii) an array of PMG structures 112P, (iv) gate spacers 114 disposedalong gate sidewalls of PMG structures 112P, (v) shallow isolationtrench (STI) regions 116 disposed on substrate 104, (vi) interlayerdielectric (ILD) layers 118A-118B, (vii) S/D contact structures 128Pdisposed on S/D regions 110P, and (viii) a gate contact structure 130Pdisposed on one of PMG structures 112P.

In some embodiments, well region 106P can represent an n-type wellregion and can include n-type dopants, such as phosphorus, arsenic, andother suitable n-type dopants. S/D regions 110P can include p-typedopants, such as boron, indium, aluminum, gallium, and other suitablep-type dopants with a doping concentration higher than the dopingconcentration of well region 106P. In some embodiments, S/D regions 110Pand PMG structure 112P interposed between S/D regions 110P can form ap-type MOSFET. In some embodiments, active P-cell 102P can have anynumber of p-type MOSFETs.

In some embodiments, PMG structure 112P can include (i) an interfacialoxide (IO) layer 120P disposed on well region 106P, (ii) a high-k (HK)gate dielectric layer 122P disposed on IO layer 120P, (iii) a pWFM layer124P disposed on HK gate dielectric layer 122P, and (iv) a gate metalfill layer 126P disposed on pWFM layer 124P. In some embodiments, IOlayer 120P can include silicon oxide (SiO_(x)), silicon germanium oxide(SiGeOx), germanium oxide (GeOx), or other suitable oxide materials. Insome embodiments, HK gate dielectric layer 122P can include (i) a high-kdielectric material, such as hafnium oxide (HfO2), titanium oxide(TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafniumsilicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate(ZrSiO2), and (ii) a high-k dielectric material having oxides of lithium(Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr),scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum(La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm),europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium(Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), (iii)other suitable high-k dielectric materials, and (iii) a combinationthereof. As used herein, the term “high-k” refers to a high dielectricconstant. In the field of semiconductor device structures andmanufacturing processes, high-k refers to a dielectric constant that isgreater than the dielectric constant of SiO2 (e.g., greater than 3.9).

In some embodiments, pWFM layer 124P can include substantially Al-free(e.g., with no Al) Ti-based or Ta-based nitrides or alloys, such astitanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold(Ti—Au) alloy, titanium copper (Ti—Cu) alloy, tantalum nitride (TaN),tantalum silicon nitride (TaSiN), tantalum gold (Ta—Au) alloy, tantalumcopper (Ta—Cu), other suitable substantially Al-free conductivematerials, and a combination thereof. In some embodiments, gate metalfill layer 126P can include a suitable conductive material, such astungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum(Mo), copper (Cu), cobalt (Co), aluminum (Al), iridium (Ir), nickel(Ni), other suitable conductive materials, and a combination thereof. Insome embodiments, gate metal fill layer 126P can include a substantiallyfluorine-free metal layer (e.g., fluorine-free W). The substantiallyfluorine-free metal layer can include an amount of fluorine contaminantsless than about 5 atomic percent in the form of ions, atoms, and/ormolecules.

In some embodiments, S/D contact structures 128P and gate contactstructure 130P can include conductive materials with low resistivity(e.g., resistivity about 50 μΩ-cm, about 40 μΩ-cm, about 30 μΩ-cm, about20 μΩ-cm, or about 10 μΩ-cm), such as cobalt (Co), tungsten (W),ruthenium (Ru), iridium (Ir), nickel (Ni), Osmium (Os), rhodium (Rh),aluminum (Al), molybdenum (Mo), other suitable conductive materials withlow resistivity, and a combination thereof. In some embodiments, gatespacers 114, STI regions 116, and ILD layers 118A-118B can include aninsulating material, such as silicon oxide, silicon nitride (SiN),silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN),silicon germanium oxide, and other suitable insulating materials.

Referring to FIGS. 1B, 1E, and 1H, in some embodiments, active N-cell102N can include (i) a well region 106N disposed within substrate 104,(ii) an array of S/D regions 110N disposed within well region 106N,(iii) an array of NMG structures 112N, (iv) gate spacers 114 disposedalong gate sidewalls of NMG structures 112N, (v) STI regions 116disposed on substrate 104, (vi) ILD layers 118A-118B, (vii) S/D contactstructures 128N disposed on S/D regions 110N, and (viii) a gate contactstructure 130N disposed on one of NMG structures 112N.

In some embodiments, well region 106N can include p-type dopants, suchas boron, indium, aluminum, gallium, and other suitable p-type dopants.S/D regions 110N can include n-type dopants, such as phosphorus,arsenic, and other suitable n-type dopants with a doping concentrationhigher than the doping concentration of well region 106N. In someembodiments, S/D regions 110N and NMG structure 112N interposed betweenS/D regions 110N can form an n-type MOSFET. In some embodiments, activeN-cell 102N can have any number of n-type MOSFETs.

In some embodiments, NMG structure 112N can include (i) an IO layer 120Ndisposed on well region 106N, (ii) a HK gate dielectric layer 122Ndisposed on IO layer 120N, (iii) a nWFM layer 124N disposed on HK gatedielectric layer 122N, and (iv) a gate metal fill layer 126N disposed onnWFM layer 124N. In some embodiments, nWFM layer 124N can includetitanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalumaluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti,Al-doped TiN, Al-doped Ta, Al-doped TaN, other suitable Al-basedconductive materials, and a combination thereof. The discussion of IOlayer 120P, HK gate dielectric layer 122P, and gate metal fill layer126P applies to IO layer 120N, HK gate dielectric layer 122N, and gatemetal fill layer 126N, unless mentioned otherwise. In some embodiments,pWFM layer 124P and gate metal fill layer 126P are different from nWFMlayer 124N and gate metal fill layer 126N. As a result, PMG structures112P and NMG structures 112N can be formed sequentially, and notsimultaneously, according to some embodiments.

Referring to FIGS. 1C, 1F, and 1I-1J, in some embodiments, dummy NP-cell102NP can include (i) an array of well regions 107P-107N disposed withinsubstrate 104, (ii) arrays of S/D regions 111P-111N disposed withinrespective well regions 107P-107N, (iii) an array of dual gatestructures 115, (iv) gate spacers 114 disposed along gate sidewalls ofdual gate structures 115, (v) STI regions 116 disposed on substrate 104,and (vi) ILD layers 118A-118B. Unlike active P-cell 102P and activeN-cell 102N, dummy NP-cell 102NP does not have S/D contact structuresand gate contact structures. The discussion of well regions 106P-106Nand S/D regions 110P-110N applies to well regions 107P-107N and S/Dregions 111P-111N, respectively, unless mentioned otherwise. In someembodiments, instead of well regions 107P and 107N of differentconductivity types, dummy NP-cell 102NP can have well regions 107P and107N of the same conductivity type or can have a well region similar towell region 106P or 106N. Similarly, in some embodiments, instead of S/Dregions 111P and 111N of different conductivity types, dummy NP-cell102NP can have S/D regions of the same conductivity type or can have anarray of S/D regions similar to S/D regions 110P or 110N. In someembodiments, dummy NP-cell 102NP does not include well regions 107P-107Nand/or S/D regions 111P-111N.

In some embodiments, each of dual gate structures 115 can include adummy PMG structure 113P and a dummy NMG structure 113N with a gate endsurface abutting a gate end surface of dummy PMG structure 113P. Theterm “gate end surface” is used herein to refer to a side surface of agate structure along a gate length (e.g., along an X-axis) of the gatestructure. The term “gate sidewall” is used herein to refer to a sidesurface of a gate structure along a gate width (e.g., along a Y-axis) ofthe gate structure. The discussion of PMG structures 112P and NMGstructures 112N applies to respective dummy PMG structures 113P anddummy NMG structures 113N, unless mentioned otherwise. In someembodiments, gate lengths GL1, GL2, GL3, and GL4 of respective PMGstructures 112P, NMG structures 112N, dummy PMG structures 113P, anddummy NMG structures 113N are substantially equal to each other. In someembodiments, gate lengths GL3 and GL4 are substantially equal to eachother, and different from respective gate lengths GL1 and GL2. In someembodiments, gate widths GW1 and GW2 are substantially equal to eachother. In some embodiments, the cell area, along an XY-plane, of dummyNP-cell 102NP can be substantially equal to or different from the cellarea, along an XY-plane of active P-cell 102P and/or active N-cell 102N.In some embodiments, the cell area, along an XY-plane, of dummy NP-cell102NP can range from about 1 μm² to about 9 μm² or other suitabledimensions. In some embodiments, S/D regions 111P and PMG structure 113Pinterposed between S/D regions 111P can form a p-type MOSFET. In someembodiments, S/D regions 111N and NMG structure 113N interposed betweenS/D regions 111N can form an n-type MOSFET.

In some embodiments, a gate top surface area, along an XY-plane, of eachdummy PMG structure 113P is substantially equal to a gate top surfacearea, along an XY-plane, of each dummy NMG structure 113N. Thus, dummyNP-cell 102NP has a gate top surface area ratio of about 1:1 between thetotal gate top surface area of dummy PMG structures 113P and the totalgate top surface area of dummy NMG structures 113N. Such balanced gatetop surface area ratio between dummy PMG and NMG structures 113P-113Ncan prevent or minimize the CMP process-related dishing effects in boththe arrays of PMG and NMG structures 112P-112N to achieve substantiallyuniform gate top surface profiles in both active P-cell 102P and activeN-cell 102N. The dishing effects can cause non-uniform gate top surfaceprofile (e.g., concave shaped profiles 132P-132N shown in FIGS. 1G-1H),which results in a mismatch between gate heights GH1 of PMG structures112P and between gate heights GH2 of NMG structures 112N, and degradesthe IC performance.

If the gate top surface area ratio is unbalanced between dummy PMG andNMG structures 113P-113N, the CMP process-related dishing effects maynot be prevented or minimized in both or either of the arrays of PMG andNMG structures 112P-112N. For example, if dummy NP-cell 102NP haspolysilicon structures or only NMG structures instead of dual gatestructures 115, the CMP process-related dishing effects can occur inactive P-cell 102P due to a polishing rate mismatch between thematerials of PMG structures 112P and the materials of polysiliconstructures or NMG structures during the fabrication of active P-cell102P. In addition, the CMP process-related dishing effects can occur inactive N-cell 102P due to a polishing rate mismatch between thematerials of NMG structures 112N and the materials of polysiliconstructures during the fabrication of active N-cell 102N.

Similarly, if dummy NP-cell 102NP has polysilicon structures or only PMGstructures instead of dual gate structures 115, the CMP process-relateddishing effects can occur in active N-cell 102P due to a polishing ratemismatch between the materials of NMG structures 112N and the materialsof polysilicon structures or PMG structures, and in active P-cell 102Ndue to a polishing rate mismatch between the materials of PMG structures112P and the materials of polysilicon structures. Thus, a balanceddistribution of dummy PMG and NMG structures 113P-113N can providematching polishing rates for both PMG and NMG structures 112P-112N forsubstantially uniform polishing of the gate top surfaces during thefabrication of active P-cell 102P and active N-cell 102N. As a result,substantially equal gate heights GH1, GH2, GH3, and GH4 of respectivePMG structures 112P, NMG structures 112N, dummy PMG structures 113P, anddummy NMG structures 113N can be achieved.

In some embodiments, to achieve the substantially uniform gate topsurface profile in active P-cell 102P, the total gate top surface areaof dummy PMG structures 113P is smaller than the total gate top surfacearea of PMG structures 112P. Similar, in some embodiments, to achievethe substantially uniform gate top surface profile in active N-cell102N, the total gate top surface area of dummy NMG structures 113N issmaller than the total gate top surface area of NMG structures 112N.

The number of well regions, S/D regions, and gate structures shown inFIGS. 1A-1I is illustrative. Active P-cell 102P, active N-cell 102N, anddummy NP-cell 102NP can have any number of well regions, S/D regions,and gate structures.

Referring to FIGS. 1K-1L, in some embodiments, the IC can include aplurality of active P-cells 102P forming an active P-cell array 100P anda plurality of active N-cells 102N forming an active N-cell array 100Nin the active device areas on substrate 104, and can include dummyNP-cells 102NP forming a dummy NP-cell array 100NP in the dummy devicearea on substrate 104. FIG. 1K illustrates top-down views of activeP-cell array 100P, active N-cell array 100N, and dummy NP-cell array100NP, according to some embodiments. FIGS. 1L-1M illustratecross-sectional views of active P-cell array 100P, active N-cell array100N, and dummy NP-cell array 100NP along lines H-H and J-J of FIG. 1K,according to some embodiments. Some of the elements of active P-cell102P, active N-cell 102N, and dummy NP-cell 102NP are not shown in FIGS.1K-1M for simplicity. Though the array sizes of active P-cell array 100Pand active N-cell array 100N are shown to be equal to each other anddifferent from the array size of dummy NP-cell array 100NP, the arraysizes of active P-cell array 100P, active N-cell array 100N, and dummyNP-cell array 100NP can be equal to or different from each other. The ICcan include any number of active P-cell array 100P, active N-cell array100N, and dummy NP-cell array 100NP. In some embodiments, distance D1between active P-cell array 100P and dummy NP-cell array 100NP anddistance D2 between active N-cell array 100N and dummy NP-cell array100NP can be equal to or different from each other, and can range fromabout 100 nm to about 1000 nm or other suitable dimensions. FIGS. 1L-1Millustrates that the balanced gate top surface area ratio between PMGand NMG structures 113P-113N in dummy NP-cell array 100NP results insubstantially uniform surface profiles and substantially equal gateheights GH1 and GH2 across PMG and NMG structures 112P-112N.

In some embodiments, instead of dummy NP-cell array 100NP, the balancedgate top surface area ratio of about 1:1 between dummy PMG and NMGstructures can be achieved with dummy NP-cell array 136NP shown in FIG.1N or dummy NP-cell array 138NP shown in FIG. 1O. Each of dummy NP-cellarrays 136NP and 138NP can include an equal number of dummy P-cells 134Pwith dummy PMG structures 135P and dummy N-cells 134N with dummy NMGstructures 135N arranged in different configurations. Thus, each ofdummy NP-cell arrays 136NP and 138NP has a gate top surface area ratioof about 1:1 between the total gate top surface area of dummy PMGstructures 135P and the total gate top surface area of dummy NMGstructures 135N. In some embodiments, dummy P-cells 134P can be similarto dummy NP-cell 102NP, except dummy P-cells 134P include PMG structures135P instead of dual gate structure 115. In some embodiments, dummyN-cells 134N can be similar to dummy NP-cell 102NP, except dummy N-cells134N include NMG structures 135N instead of dual gate structure 115. Thediscussion of PMG and NMG structures 134P-134N applies to PMG and NMGstructures 112P-112N, unless mentioned otherwise.

FIGS. 2A-2C illustrate top-down views of an active P-cell 202P, anactive N-cell 202N, and a dummy NP-cell 202NP, respectively, of the IC(not shown), according to some embodiments. FIGS. 2D-2F illustratecross-sectional views of active P-cell 202P, active N-cell 202N, anddummy NP-cell 202NP along lines A-A, B-B, and C-C of FIGS. 2A-2C,according to some embodiments. FIGS. 2G-2J illustrate cross-sectionalviews of active P-cell 202P, active N-cell 202N, and dummy NP-cell 202NPalong lines D-D, E-E, F-F, and G-G of FIGS. 2A-2C, according to someembodiments. FIGS. 2K-2M illustrate isometric views of regions A-C ofrespective FIGS. 2A-2C, according to some embodiments. FIGS. 2D-2Millustrate cross-sectional and isometric views with additionalstructures that are not shown in FIGS. 2A-2C for simplicity. Thediscussion of elements in FIGS. 1A-1M and 2A-2M with the sameannotations applies to each other, unless mentioned otherwise.

Referring to FIGS. 2A-2M, active P-cell 202P, active N-cell 202N, anddummy NP-cell 202NP can be disposed on different regions of substrate104 of the IC. Active P-cell 202P and active N-cell 202N can be disposedin the active device areas of the IC and dummy NP-cell 202NP can bedisposed in the dummy device area of the IC. In some embodiments, activeP-cell 202P, active N-cell 202N, and dummy NP-cell 202NP can be arrangedin a row or column on substrate 204, and dummy NP-cell 202NP can bedisposed between active P-cell 202P and active N-cell 202N. Unlikeactive P-cell 202P and active N-cell 202N, dummy NP-cell 202NP is notelectrically coupled to a power supply and is electrically isolated fromother structures of the IC. In some embodiments, the IC can include anynumber of active P-cell 202P, active N-cell 202N, and dummy NP-cell202NP. In some embodiments, dummy NP-cells, such as dummy NP-cell 202NP,can be disposed surrounding one or more of active P-cell 202P and/oractive N-cell 202N.

Referring to FIGS. 2A-2B, 2D-2E, 2G-2H, and 2K-2I, in some embodiments,active P-cell 202P and active N-cell 202N can include (i) fin structures206P and 206N disposed on substrate 104, (ii) an array of S/D regions210P and 210N disposed on respective fin structures 206P and 206N, (iii)an array of PMG structures 212P and NMG structures 212N disposed on theportions of fin structures 206P and 206N that do not have S/D regions210P and 210N, (iv) gate spacers 114 disposed along gate sidewalls ofPMG structures 212P and NMG structures 212N, (v) STI regions 116disposed on substrate 104, (vi) ILD layers 118A-118B, (vii) etch stoplayer 217, (viii) S/D contact structures 228P and 228N disposed onrespective S/D regions 210P and 210N, and (ix) gate contact structures230P and 230N disposed on respective PMG structures 212P and NMGstructures 212N.

In some embodiments, fin structures 206P-206N can include a materialsimilar to substrate 104 and extend along an X-axis. In someembodiments, S/D regions 210P can include an epitaxially-grownsemiconductor material, such as Si and SiGe, and can include p-typedopants, such as boron, indium, aluminum, gallium, and other suitablep-type dopants. In some embodiments, S/D regions 210N can include anepitaxially-grown semiconductor material, such as Si, and can includen-type dopants, such as phosphorus, arsenic, and other suitable n-typedopants. In some embodiments, S/D regions 210P and PMG structures 212Pinterposed between S/D regions 210P can form p-type finFETs. In someembodiments, S/D regions 210N and NMG structures 212N interposed betweenS/D regions 210N can form n-type finFETs. The discussion of PMG and NMGstructures 112P-112N, S/D contact structures 128P-128N, and gate contactstructures 130P-130N applies to PMG and NMG structures 212P-212N, S/Dcontact structures 228P-228N, and gate contact structures 230P-230N,unless mentioned otherwise. In some embodiments, ESL 217 can include aninsulating material, such as silicon oxide, silicon nitride (SiN),silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN),silicon germanium oxide, and other suitable insulating materials.

Referring to FIGS. 2C, 2F, 2I-2J, and 2M, in some embodiments, dummyNP-cell 202NP can include (i) fin structures 207P and 207N disposed onsubstrate 104, (ii) arrays of S/D regions 211P-211N disposed onrespective fin structures 207P-207N, (iii) an array of dual gatestructures 215, (iv) gate spacers 114 disposed along gate sidewalls ofdual gate structures 215, (v) STI regions 116 disposed on substrate 104,(vi) ILD layers 118A-118B, and (vii) etch stop layer 217. Unlike activeP-cell 202P and active N-cell 202N, dummy NP-cell 202NP does not haveS/D contact structures and gate contact structures. The discussion offin structures 206P-206N and S/D regions 210P-210N applies to finstructures 207P-207N and S/D regions 211P-211N, respectively, unlessmentioned otherwise. In some embodiments, dummy NP-cell 202NP can haveS/D regions of the same conductivity type. The discussion of dual gatestructures 115 applies to dual gate structures 215, unless mentionedotherwise.

In some embodiments, each of dual gate structures 215 can include adummy PMG structure 213P and a dummy NMG structure 213N with a gate endsurface abutting a gate end surface of dummy PMG structure 213P. In someembodiments, S/D regions 211P and PMG structures 213P interposed betweenS/D regions 211P can form p-type finFETs. In some embodiments, S/Dregions 211N and NMG structures 213N interposed between S/D regions 211Ncan form n-type finFETs. The discussion of dummy PMG structures 113P anddummy NMG structures 113N applies to respective dummy PMG structures213P and dummy NMG structures 213N, unless mentioned otherwise. Similarto dummy NP-cell 102NP, dummy NP-cell 202NP has a gate top surface arearatio of about 1:1 between the total gate top surface area of dummy PMGstructures 213P and the total gate top surface area of dummy NMGstructures 213N. As a result, substantially uniform gate top surfaceprofiles in both active P-cell 202P and active N-cell 202N, andsubstantially equal gate heights GH1 and GH2 of respective PMGstructures 212P and NMG structures 212N can be achieved.

In some embodiments, to achieve the substantially uniform gate topsurface profile in active P-cell 202P, the total gate top surface areaof dummy PMG structures 213P is smaller than the total gate top surfacearea of PMG structures 212P. Similar, in some embodiments, to achievethe substantially uniform gate top surface profile in active N-cell202N, the total gate top surface area of dummy NMG structures 213N issmaller than the total gate top surface area of NMG structures 212N. Thenumber of fin structures, S/D regions, and gate structures shown inFIGS. 2A-2M is illustrative. Active P-cell 202P, active N-cell 202N, anddummy NP-cell 202NP can have any number of fin structures, S/D regions,and gate structures. In some embodiments, a plurality of active P-cells202P, active N-cells 202N, and dummy NP-cells 202NP can form arrayssimilar to active P-cell array 100P, active N-cell array 100N, and dummyNP-cell array 100NP.

FIG. 3 is a flow diagram of an example method 300 for fabricating activeP-cell 102P, active N-cell 102N, and dummy cell 102NP on substrate 104,according to some embodiments. For illustrative purposes, the operationsillustrated in FIG. 3 will be described with reference to the examplefabrication process for fabricating active P-cell 102P, active N-cell102N, and dummy cell 102NP as illustrated in FIGS. 4A-13G. FIGS. 4A-13Gare cross-sectional views of active P-cell 102P, active N-cell 102N, anddummy NP-cell 102NP along lines A-A, B-B, C-C, D-D, E-E, F-F, and G-G ofFIGS. 1A-1C, according to some embodiments. Operations can be performedin a different order or not performed depending on specificapplications. It should be noted that method 300 may not produce acomplete active P-cell 102P, active N-cell 102N, and dummy cell 102NP ofthe IC. Accordingly, it is understood that additional processes can beprovided before, during, and after method 300, and that some otherprocesses may only be briefly described herein. Elements in FIGS. 4A-13Gwith the same annotations as elements in FIGS. 1A-1J are describedabove.

In operation 305, well regions, S/D regions, and polysilicon structuresof an active P-cell, an active N-cell, and a dummy NP-cell are formed.For example, as shown in FIGS. 4A-4G, well regions 106P, 106N, 107P, and107N, polysilicon structures 412, and S/D regions 110P, 110N, 111P, and111N are formed. The formation of polysilicon structures 412 can befollowed by the formation of gate spacers 114, which can be followed bythe formation of S/D regions 110P, 110N, 111P, and 111N. The formationof S/D regions 110P, 110N, 111P, and 111N can be followed by theformation of ILD layer 118A.

Referring to FIG. 3 , in operation 310, PMG structures are selectivelyformed in the active P-cell and the dummy NP-cell. For example, asdescribed with reference to FIGS. 5A-8G, PMG structures 112P and 113Pare selectively formed in active P-cell 102P and dummy NP-cell 102NP.The formation of PMG structures 112P and 113P can include sequentialoperations of (i) forming a patterned masking layer 540 (e.g., aphotoresist layer) on the structures of FIGS. 4B, 4C, 4E, and 4G to formthe structures of FIGS. 5B, 5C, 5E, and 5G, (ii) forming gate openings612P and 612NP (shown in FIGS. 6A, 6C, 6D, and 6F) substantially at thesame by etching polysilicon structures 412 from the structures of FIGS.5A and 5D, and by etching the exposed portions of polysilicon structures412 from the structures of FIGS. 5C and 5F, (iii) removing patternedmasking layer 540, (iv) forming IO layers 120P on well regions 106P and107P, as shown in FIGS. 7A, 7C, 7D, and 7F, (v) depositing HK gatedielectric layer 122P on the structures of FIGS. 7A-7G, (vi) depositingpWFM layer 124P on HK gate dielectric layer 122P, (vii) depositing gatemetal fill layer 126P on pWFM layer 124P, and (viii) performing a CMPprocess on the deposited HK gate dielectric layer 122P, pWFM layer 124P,and gate metal fill layer 126P to form the structures of FIGS. 8A-8G. Insome embodiments, the portion of patterned masking 540 on the structuresof dummy NP-cell 102NP cover about 50% of the total top surface area ofpolysilicon structures 412, as shown in FIG. 5C.

Referring to FIG. 3 , in operation 315, NMG structures are selectivelyformed in the active N-cell and the dummy NP-cell. For example, asdescribed with reference to FIGS. 9A-12G, NMG structures 112N and 113Nare selectively formed in active N-cell 102N and dummy NP-cell 102NP.The formation of NMG structures 112N and 113N can include sequentialoperations of (i) forming a patterned masking layer 940 (e.g., aphotoresist layer) on the structures of FIGS. 8A, 8C, 8D, and 8F to formthe structures of FIGS. 9A, 9C, 9D, and 9F, (ii) forming gate openings1012N and 1012NP (shown in FIGS. 10B, 10C, 10E, and 10G) substantiallyat the same by etching polysilicon structures 412 from the structures ofFIGS. 9B and 9E, and by etching the exposed remaining portions ofpolysilicon structures 412 from the structures of FIGS. 9C and 9G, (iii)removing patterned masking layer 940, (iv) forming TO layers 120N onwell regions 106N and 107N, as shown in FIGS. 11B, 11C, 11E, and 11G,(v) depositing HK gate dielectric layer 122N on the structures of FIGS.11A-11G, (vi) depositing nWFM layer 124N on HK gate dielectric layer122N, (vii) depositing gate metal fill layer 126N on nWFM layer 124N,and (viii) performing a CMP process on the deposited HK gate dielectriclayer 122N, nWFM layer 124N, and gate metal fill layer 126N to form thestructures of FIGS. 12A-12G.

Referring to FIG. 3 , in operation 320, contact structures areselectively formed on the S/D regions and the PMG and NMG structures ofthe active P-cell and the active N-cell. For example, as shown in FIGS.13A-13B and 13D-13E, S/D contact structures 128P-128N are formed on S/Dregions 110P-110N and gate contact structures 130P-130N are formed onPMG and NMG structures 112P-112N.

In some embodiments, operations of method 300 can be performed to form aplurality of active P-cells 102P, active N-cells 102N, and dummyNP-cells 102NP to form the respective active P-cell array 100P, activeN-cell array 100N, and dummy NP-cell array 100NP.

FIG. 14 is a flow diagram of an example method 1400 for fabricatingactive P-cell 202P, active N-cell 202N, and dummy cell 202NP onsubstrate 104, according to some embodiments. For illustrative purposes,the operations illustrated in FIG. 14 will be described with referenceto the example fabrication process for fabricating active P-cell 202P,active N-cell 202N, and dummy cell 202NP as illustrated in FIGS.15A-22C. FIGS. 15A-22C are cross-sectional views of active P-cell 202P,active N-cell 202N, and dummy NP-cell 202NP along lines A-A, B-B, andC-C of FIGS. 2A-2C, according to some embodiments. Operations can beperformed in a different order or not performed depending on specificapplications. It should be noted that method 1400 may not produce acomplete active P-cell 202P, active N-cell 202N, and dummy cell 202NP ofthe IC. Accordingly, it is understood that additional processes can beprovided before, during, and after method 1400, and that some otherprocesses may only be briefly described herein. Elements in FIGS.15A-22C with the same annotations as elements in FIGS. 2A-2M aredescribed above.

In operation 1405, fin structures, S/D regions, and polysiliconstructures of an active P-cell, an active N-cell, and a dummy NP-cellare formed. For example, as shown in FIGS. 15A-15C, fin structures 206P,206N, 207P, and 207N and polysilicon structures 1512 are formed. Inaddition, S/D regions 210P, 210N, 211P, and 211N (not visible in thecross-sectional views of FIGS. 15A-15C) are epitaxially grown on theportions of fin structures 206P, 206N, 207P, and 207N that are notcovered by polysilicon structures 1512. The formation of polysiliconstructures 1512 can be followed by the formation of gate spacers 114,which can be followed by the formation of S/D regions 210P, 210N, 211P,and 211N. The formation of S/D regions 210P, 210N, 211P, and 211N can befollowed by the formation of ILD layer 118A and ESL 217 (not visible inthe cross-sectional views of FIGS. 15A-15C).

Referring to FIG. 14 , in operation 1410, PMG structures are selectivelyformed in the active P-cell and the dummy NP-cell. For example, asdescribed with reference to FIGS. 16A-18C, PMG structures 212P and 213Pare selectively formed in active P-cell 202P and dummy NP-cell 202NP.The formation of PMG structures 212P and 213P can include sequentialoperations of (i) forming gate openings 1612P and 1612NP (shown in FIGS.16A and 16C) substantially at the same time by etching polysiliconstructures 1512 from the structure of FIG. 15A, and by etching theexposed portions of polysilicon structures 1512 from the structure ofFIG. 15C, (ii) forming IO layers 120P on fin structures 206P and 207P,as shown in FIGS. 17A and 17C, (iii) depositing HK gate dielectric layer122P on the structures of FIGS. 17A-17C, (vi) depositing pWFM layer 124Pon HK gate dielectric layer 122P, (iv) depositing gate metal fill layer126P on pWFM layer 124P, and (v) performing a CMP process on thedeposited HK gate dielectric layer 122P, pWFM layer 124P, and gate metalfill layer 126P to form the structures of FIGS. 18A-18C.

Referring to FIG. 14 , in operation 1415, NMG structures are selectivelyformed in the active N-cell and the dummy NP-cell. For example, asdescribed with reference to FIGS. 19A-21C, NMG structures 212N and 213Nare selectively formed in active N-cell 202N and dummy NP-cell 202NP.The formation of NMG structures 212N and 213N can include sequentialoperations of (i) forming gate openings 1912N and 1912NP (shown in FIGS.19B and 19C) substantially at the same by etching polysilicon structures1512 from the structure of FIG. 19B, and by etching the exposedremaining portions of polysilicon structures 1512 from the structure ofFIG. 19C, (ii) forming IO layers 120N on fin structures 206N and 207N,as shown in FIGS. 20B and 20C, (iii) depositing HK gate dielectric layer122N on the structures of FIGS. 20A-20C, (vi) depositing nWFM layer 124Non HK gate dielectric layer 122N, (vii) depositing gate metal fill layer126N on nWFM layer 124N, and (viii) performing a CMP process on thedeposited HK gate dielectric layer 122N, nWFM layer 124N, and gate metalfill layer 126N to form the structures of FIGS. 21A-21C.

Referring to FIG. 14 , in operation 1420, contact structures areselectively formed on the S/D regions and the PMG and NMG structures ofthe active P-cell and the active N-cell. For example, as shown in FIGS.22A-22B gate contact structures 230P-230N are formed on PMG and NMGstructures 212P-212N. S/D contact structures 228P-228N (not visible inthe cross-sectional views of FIGS. 22A-22C) are formed on S/D regions210P-210N.

The present disclosure provides example integrated circuits (ICs) withactive and dummy device cell arrays (e.g., active P-cell array 100P,active N-cell array 100N, and dummy NP-cell arrays 100NP, 136NP, and138NP) in respective active and dummy device areas, and example methods(e.g., methods 300 and 1400) of fabricating the same. The example IC caninclude n- and/or p-type active device cell arrays. The n-type activedevice cell arrays can include arrays of active N-cells (e.g., activeN-cells 102N and 202N). Each of the active N-cells can include one ormore electrically active n-type FETs (e.g., NMOSFETs, N-finFETs, orgate-all-around (GAA) NFETs) and/or n-type structures, such as n-typeS/D regions (e.g., S/D regions 110N and 210N) and NMG structures (e.g.,NMG structures 112N and 212N). The p-type active device cell arrays caninclude arrays of active P-cells (e.g., active P-cells 102P and 202P).Each of the active P-cells can include one or more electrically activep-type FETs (e.g., PMOSFETs, P-finFETs, or gate-all-around (GAA) PFETs)and/or p-type structures, such as p-type S/D regions (e.g., S/D regions110P and 210P) and PMG structures (e.g., PMG structures 112P and 212P).The active N-cells and P-cells can further include contact structures(e.g., S/D contact structures 128P-128N and 228P-228N, gate contactstructures 130P-130N and 230P-230N) disposed on one or more S/D regionsand gate structures.

The dummy device cell arrays can be disposed adjacent to or surroundingthe active device cell arrays and can include dummy N-cells and P-cells,and/or NP-cells (e.g., dummy N-cells 134N, dummy P-cells 134P, and dummyNP cells 102NP-202NP). Unlike the active N-cells and P-cells, the dummyN-cells, P-cells, and NP-cells do not include contact structures and/orcontact landing pads or regions on the S/D regions and/or gatestructures. The dummy device cell arrays can be formed and arranged in amanner to achieve a substantially uniform surface profile across thegate structures in both active P- and N-cell arrays. Each dummy devicecell array can be formed with a gate surface area ratio of about 1:1between the total top surface area of the dummy NMG structures and thetotal top surface area of the dummy PMG structures to achieve thesubstantially uniform surface profile. Such balanced gate surface arearatio between the dummy NMG and PMG structures can prevent or minimizethe CMP process-related dishing effects during the formation of theactive NMG and PMG structures. The balanced distribution of the dummyNMG and PMG structures provide matching polishing rates for the activeNMG and PMG structures, and consequently prevent or minimize the CMPprocess-related dishing effects.

In some embodiments, each of the dummy device cell arrays (e.g., dummyNP-cell array 136NP and 138NP) can be formed with an equal number ofdummy N-cells (e.g., dummy N-cells 134N) and dummy P-cells (e.g., dummyP-cells 134P) to achieve the balanced gate surface area ratio. In someembodiments, the dummy N-cells and P-cells can be arranged in an arrayconfiguration or in an alternating configuration with respect to eachother. The dummy N-cells can have dummy NMG structures (e.g., dummy NMGstructures 135N) that are equal in number to the dummy PMG structures(e.g., dummy PMG structures 135P) of the dummy P-cells. In someembodiments, the dummy NMG and PMG structures can have gate dimensions(e.g., gate length, gate width, and gate height) that are substantiallyequal to each other. In some embodiments, the dummy NMG structures canhave a total top surface area that is substantially equal to the totaltop surface area of the dummy PMG structures. In some embodiments, eachof the dummy device cell arrays (e.g., dummy NP-cell array 100NP) can beformed with arrays of dummy NP-cells (e.g., dummy NP-cells 102NP) havingan equal number of dummy NMG and PMG structures (e.g., dummy NMG and PMGstructures 113N-113P) to achieve the balanced gate surface area ratio.

In some embodiments, an integrated circuit includes a substrate, anactive device cell, and a dummy device cell. The active device cellincludes an array of source/drain (S/D) regions of a first conductivitytype disposed on or within the substrate and an array of gate structureswith a first gate fill material disposed on the substrate. The dummydevice cell includes a first array of S/D regions of the firstconductivity type disposed on or within the substrate, a second array ofS/D regions of a second conductivity type disposed on or within thesubstrate, and an array of dual gate structures disposed on thesubstrate. Each of the dual gate structures includes the first gate fillmaterial and a second gate fill material that is different from thefirst gate fill material.

In some embodiments, an integrated circuit includes a substrate, firstand second active source/drain (S/D) regions disposed on or within thesubstrate, an active gate structure with a gate fill layer disposed onthe substrate, first and second dummy S/D regions disposed on or withinthe substrate, and a dummy gate structure disposed on the substrate. Thedummy gate structure includes a first gate fill layer and a second gatefill layer that is different from the first gate fill layer. The firstgate fill layer has a first top surface area and the second gate filllayer has a second top surface area that is substantially equal to thefirst top surface area.

In some embodiments, a method includes forming first and second finstructures on a substrate, forming first and second source/drain (S/D)regions on the first and second fin structures, respectively, formingfirst and second polysilicon structures on the first and second finstructures, respectively, replacing the first polysilicon structure anda first portion of the second polysilicon structure with a first metallayer, polishing the first metal layer at a first polishing rate,replacing a second portion of the second polysilicon structure with asecond metal layer that is different from the first metal layer, andpolishing the second metal layer at a second polishing rate that isdifferent from the first polishing rate.

The foregoing disclosure outlines features of several embodiments sothat those skilled in the art may better understand the aspects of thepresent disclosure. Those skilled in the art should appreciate that theymay readily use the present disclosure as a basis for designing ormodifying other processes and structures for carrying out the samepurposes and/or achieving the same advantages of the embodimentsintroduced herein. Those skilled in the art should also realize thatsuch equivalent constructions do not depart from the spirit and scope ofthe present disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A method, comprising: forming first and secondfin structures on a substrate; forming first and second source/drain(S/D) regions on the first and second fin structures, respectively;forming first and second polysilicon structures on the first and secondfin structures, respectively; replacing the first polysilicon structureand a first portion of the second polysilicon structure with a firstmetal layer; polishing the first metal layer at a first polishing rate;replacing a second portion of the second polysilicon structure with asecond metal layer that is different from the first metal layer; andpolishing the second metal layer at a second polishing rate that isdifferent from the first polishing rate.
 2. The method of claim 1,wherein replacing the first polysilicon structure and the first portionof the second polysilicon structure comprises forming a masking layer ona top surface of the second portion of the second polysilicon structure.3. The method of claim 1, wherein replacing the first polysiliconstructure and the first portion of the second polysilicon structurecomprises depositing a dielectric layer on the first and second finstructures and along a sidewall of the second portion of the secondpolysilicon structure.
 4. The method of claim 3, wherein replacing thefirst polysilicon structure and the first portion of the secondpolysilicon structure further comprises depositing the first metal layeron the dielectric layer.
 5. The method of claim 1, wherein forming thefirst and second fin structures comprises forming the first and secondfin structures substantially parallel to each other.
 6. The method ofclaim 1, wherein forming the first and second polysilicon structurescomprises forming the first and second polysilicon structuressubstantially parallel to each other.
 7. The method of claim 1, furthercomprising forming a third fin structure on the substrate andsubstantially parallel to the first and second fin structures, whereinthe second portion of the second polysilicon structure is formed on thethird fin structure.
 8. The method of claim 1, wherein replacing thesecond portion of the second polysilicon structure comprises depositinga dielectric layer along a sidewall of the first metal layer.
 9. Themethod of claim 8, wherein replacing the second portion of the secondpolysilicon structure further comprises depositing the second metallayer on the dielectric layer.
 10. The method of claim 1, whereinreplacing the first polysilicon structure and the first portion of thesecond polysilicon structure comprises performing an oxidation processon the first and second fin structures.
 11. A method, comprising:forming first, second, and third fin structures on a substrate; forminga first polysilicon structure on the first fin structure; forming asecond polysilicon structure comprising a first polysilicon portion onthe second fin structure and a second polysilicon portion on the thirdfin structure; replacing the first polysilicon structure with a firstgate structure; replacing, at a same time as replacing the firstpolysilicon structure, the first polysilicon portion with a second gatestructure; and replacing the second polysilicon portion with a thirdgate structure after replacing the first polysilicon portion.
 12. Themethod of claim 11, wherein forming the first, second, and third finstructures comprises forming the first, second, and third fin structuressubstantially parallel to each other.
 13. The method of claim 11,wherein forming the first and second polysilicon structures comprisesforming the first and second polysilicon structures substantiallyparallel to each other.
 14. The method of claim 11, wherein replacingthe first polysilicon portion comprises depositing a gate dielectriclayer of the second gate structure on the second fin structure and alonga sidewall of the second polysilicon portion.
 15. The method of claim11, wherein replacing the second polysilicon portion comprisesdepositing a gate dielectric layer of the third gate structure on thethird fin structure and along a sidewall of the second gate structure.16. The method of claim 11, wherein replacing the first polysiliconportion comprises forming a masking layer on the second polysiliconportion.
 17. A method, comprising: forming first and second n-typesource/drain (S/D) regions in a substrate; forming first and secondp-type S/D regions disposed in the substrate; forming a polysiliconstructure comprising a first polysilicon portion between the first andsecond n-type S/D regions and a second polysilicon portion between thefirst and second p-type S/D regions; replacing the first polysiliconportion with a first gate structure; and replacing the secondpolysilicon portion with a second gate structure in contact with asidewall of the first gate structure.
 18. The method of claim 17,wherein replacing the first polysilicon portion comprises forming amasking layer on the second polysilicon portion.
 19. The method of claim17, wherein replacing the first polysilicon portion comprises depositinga gate dielectric layer of the first gate structure along a sidewall ofthe second polysilicon portion.
 20. The method of claim 17, whereinreplacing the second polysilicon portion comprises depositing a gatedielectric layer of the second gate structure along a sidewall of thefirst gate structure.